The present invention relates to forming a flip chip semiconductor package on a leadframe, and more particularly to forming a flip chip semiconductor package on a bare copper leadframe.
In semiconductor packaging, a relatively sensitive and difficult to handle semiconductor die is encapsulated in a package with external connections. Packaging allows the semiconductor die to be more conveniently handled, and it also allows external circuitry to be easily coupled thereto.
A known method of semiconductor packaging employs a plated leadframe. A leadframe is a patterned sheet of metal, typically copper, that has been plated, usually with silver, nickel or palladium. Plating is necessary to prevent the copper from oxidizing, and to provide a surface to which solder will adhere or, when employing wire bonding, gold or aluminum can be bonded. The pattern of the sheet of metal provides a leadframe for forming a semiconductor package.
Typically, the leadframe includes a flag portion for mounting a semiconductor die with the back of the die being bonded to the flag portion or paddle; and lead portions extending inwardly towards the flag portion. During the packaging process, lengths of wire are bonded between pads on the die and the lead portions, and subsequently the die, flag portion, lengths of wire and part of the lead portions are encapsulated, usually in mold compound; leaving parts of the lead portions exposed for external electrical connections.
Currently, plated leadframes for forming flip chip semiconductor packages have leads with inner lead portions and outer lead portions. The inner lead portions are arranged in a pattern with interconnect locations on the inner lead portions matching the pattern of pads on a semiconductor die. The semiconductor die is bumped with copper posts extending from pads on the die, and solder balls are attached to the free ends of the copper posts.
U.S. patent application Ser. No. 09/564,382 by Francisca Tung, filed on Apr. 27, 2000, titled xe2x80x9cImproved Pillar Connections For Semiconductor Chips and Method Of Manufacturexe2x80x9d, and Continuation-In-Part U.S. patent application Ser. No. (Not yet assigned) by Francisca Tung, filed on Apr. 26, 2000 titled xe2x80x9cImproved Pillar Connections For Semiconductor Chips and Method Of Manufacturexe2x80x9d, and assigned to a common assignee as this patent application, teaches forming pillar structures as described herein. These patent applications are incorporated by reference.
During assembly, flux is either printed on the interconnect locations on the leadframe or the solder balls are dipped in flux. After fluxing, the semiconductor die is flipped over, and placed on the leadframe. The solder balls abutting the interconnect locations on the inner lead portions and the flux wetting the interconnect locations and the solder balls. The assembly is then reflowed.
Under elevated reflow temperatures, the flux cleans the plated surface of the interconnect locations, and the solder balls melt and adhere to the interconnect locations. Thus, forming solder interconnects between the free ends of the copper posts on the semiconductor die, and the interconnect locations on the leadframe.
After reflow, when normal flux is used the assembly is cleaned to remove residual flux and encapsulated in mold compound. However, when no-clean flux is employed, the cleaning step is not required. The resultant package is known as a flip chip on leadframe semiconductor package.
A disadvantage of this process is the need for a plated leadframe as plating adds to the cost of the package. Another disadvantage is, when the solder balls melt, the molten solder flows across the surface of the lead portions as there is nothing on the plated surface of the leadframe to control or inhibit the flow of the molten solder. This flow of solder is often referred to as overrun, and results in a variety of adverse effects in such flip chip semiconductor packages form on leadframe.
A first concern is, when the solder flows away from an interconnect location, the respective interconnect has less solder than required to provide a reliable electrical connection. A second concern is, interconnects with the reduced amount of solder do not support the semiconductor die evenly. Consequently, the planarity of the semiconductor die on the leadframe can be adversely affected, and a non-planar die can give rise to shorting between copper posts on the die. This condition is referred to as a collapsed die.
A third concern is the overrun results in solder flowing over the edges and onto the opposite surface of the lead portions. Later, during molding the mold compound will not adhere well to the affected surfaces. A fourth concern is known as wicking. Wicking occurs when a lead portion on a leadframe is shaped such that there is a small gap between the side of a downset die and the lead, and where there is an interconnect location close to the edge of the die. In this arrangement, the solder from the interconnect location can flow along the lead and, through capillary action, flow upwards through the small gap.
In an effort to reduce costs of flip chip semiconductor packages on leadframe, un-plated or bare copper leadframes, simply referred to as copper leadframes, have been tried. However, to a large extent, the copper leadframes suffered the same disadvantages discussed hereinabove, as the plated leadframe. In addition, copper tends to oxidize when left exposed and solder cannot adhere well to copper oxide.
The present invention seeks to provide a method for forming a flip chip semiconductor package, which overcomes or at least reduces the abovementioned problems of the prior art.
Accordingly, in one aspect, the present invention provides a method for forming a flip chip semiconductor package, the method comprising the steps of:
a) providing a patterned layer of metal conductors having a first surface, wherein the first surface has a pattern of interconnect locations thereon;
b) forming a layer of passivation on the first surface of the patterned layer of metal conductors;
c) providing a semiconductor die having a first surface with a pattern of pads thereon, wherein reflowable conductive deposits are disposed on the pads;
d) selectively disposing a passivation cleaner;
e) placing the semiconductor die on the patterned layer of metal conductors to form an assembly, wherein the reflowable conductive deposits abut portions of the layer of passivation, wherein the reflowable conductive deposits are adjacent the pattern of interconnect locations, and wherein the passivation cleaner adheres to the reflowable conductive deposits and the portions of the layer of passivation; and
f) reflowing the assembly, wherein the passivation cleaner substantially removes the portions of the layer of passivation from the patterned layer of metal conductors, and wherein the reflowable conductive deposits form conductive interconnects between the pads on the semiconductor die and the interconnect locations on the patterned layer of metal conductors.
In another aspect, the present invention provides a method for forming a flip chip semiconductor package, the method comprising the steps of:
a) providing a patterned layer of metal conductors having a first surface, wherein the first surface has a pattern of interconnect locations thereon;
b) forming a layer of passivation on the first surface of the patterned layer of metal conductors;
c) providing a semiconductor die having a first surface with a pattern of pads thereon, wherein electrical conductors extend from the pads, and wherein solder deposits are disposed on free ends of the electrical conductors;
d) selectively disposing flux;
e) placing the semiconductor die on the patterned layer of metal conductors to form an assembly, wherein the solder deposits abut portions of the layer of passivation, wherein the solder deposits are adjacent the pattern of interconnect locations, and wherein the flux adheres to the solder deposits and the portions of the layer of passivation; and
f) reflowing the assembly, wherein the flux substantially removes the portions of the layer of passivation from the patterned layer of metal conductors, wherein the solder deposits form solder interconnects between the electrical conductors on the semiconductor die and the interconnect locations on the patterned layer of metal conductors, and wherein the layer of organic material vaporizes and provides passivation while vaporizing.